• Synchronous digital design is well understood; the design methodology and flow are established; and tool vendors provide a plethora of design environments that aid in design, verification, synthesis, and testing. Even though ample problems still exist because of size, complexity, power consumption, manufacturing variations, and validation cost, using synchronous abstraction and measuring clock-cycle computation delay simplify design methodology and are deeply embedded in current design practices. So, is there a way to avoid a GALS-based design and remain entirely in the world of synchrony?
• It may be possible to remain in the world of synchrony by elasticizing the interconnects and computation blocks through latency-insensitive (synchronous elastic) protocols. Elastic designs remain synchronous but allow flexible changes in design latencies and can be viewed as discretized implementations of asynchronous protocols. Are there general theories for designing latency-insensitive systems, and what are the best ways of implementing such systems? Would they alleviate the need for a GALS approach to some extent or could they be used in the context of multiple clock domains?
• There are many different ways of designing GALS-based systems using different clocking disciplines (for example, fully asynchronous local clocks; synchronous sources with clock transfers from sender to receiver; pausible clocks; and harmonic, synchronous multiclocks). Some of these disciplines make the clock domains completely independent at the cost of synchronization problems between the domains. Others require satisfying some timing constraints in clock generation but remove the synchronization problem. Which disciplines are preferable and for which design classes?
• Asynchronous circuit design has been around for a long time. However, despite some advantages (for example, improved average-case performance and reduced electromagnetic interference), this design approach has not caught on in industry on a grand scale. The tools and design methodologies for asynchronous designs are not amply available from EDA vendors. Will we face the same problem with GALS design?
• Given that we have tools for test and verification of synchronous designs, can we design synchronously and then partition the system into synchronous islands, so that the GALS implementation of the design will simply be a refinement of the original validated design while still preserving the correctness of this design?
• What signaling and clocking issues must be solved to correctly implement high-level GALS protocols? Synchronization failures may be endemic in this kind of design. Can the absence of such problems be guaranteed for the eventual silicon implementations?
• Since the protocols between synchronous IP blocks will be self-timed, latency tolerant, and not necessarily clock driven, the simplicity of central control could be lost in GALS systems, leading to issues of deadlock and other distributed-system phenomena. How can we guarantee the absence of such problems?
Mike Kishinevsky is a principal engineer at Strategic CAD Labs of Intel, where he is responsible for front-end design. His research interests include high-level and asynchronous design, reactive systems, and models of concurrency. Kishinevsky has a PhD in computer science from the Electrotechnical University of St. Petersburg. He is a senior member of the IEEE.
Sandeep K. Shukla is an associate professor in the Department of Electrical and Computer engineering at Virginia Tech. He is also founder and deputy director of the Center for Embedded Systems for Critical Applications, and he directs the Fermat (Formal Engineering Research with Models, Abstractions, and Transformations) research lab. His research interests include formal methods for system design, reliability of nanoscale architectures, embedded-software design and verification, and system-level design languages. Shukla has a PhD in computer science from the State University of New York at Albany. He is a College of Engineering Faculty Fellow at Virginia Tech and is a senior member of the IEEE and the ACM. He is on the editorial boards of IEEE Design & Test and IEEE Transactions on Industrial Informatics.
Kenneth S. Stevens is an associate professor in the Department of Electrical and Computer Engineering at the University of Utah. His research interests include asynchronous circuits, VLSI, architecture and design, hardware synthesis and verification, and timing analysis. Stevens has a PhD in computer science from the University of Calgary. He is a senior member of the IEEE.