Issue No.05 - September-October (2007 vol.24)
Paul Teehan , University of British Columbia
Mark Greenstreet , University of British Columbia
Guy Lemieux , University of British Columbia
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2007.151
Large digital systems increasingly feature global asynchronous interconnects and multiple clock domains. Thus, they are globally asynchronous, locally synchronous (GALS) designs. The authors identify three emerging GALS design styles, present examples of each, survey related research, and describe practical implementation issues. They also discuss the obstacles hindering widespread adoption of GALS design and conclude that CAD support will soon follow the increasing industry interest in this area.
globally asynchronous, locally synchronous (GALS); clock domains; synchronization; pausible clocks; asynchronous; loosely synchronous
Paul Teehan, Mark Greenstreet, Guy Lemieux, "A Survey and Taxonomy of GALS Design Styles", IEEE Design & Test of Computers, vol.24, no. 5, pp. 418-428, September-October 2007, doi:10.1109/MDT.2007.151