The Community for Technology Leaders
RSS Icon
Issue No.05 - September-October (2007 vol.24)
pp: 486-493
Architecture and design of debugging logic for high-speed processor chips is somewhat of an art form, requiring the design of logic intended to isolate events that have not occurred. In fact, the goal is for such events never to occur, but history has shown that there are usually a few problems that need debugging. The Cell Broadband Engine processor is a new multicore processor that pushed the design limits. This article explores some of the debugging features that were added to the Cell Broadband Engine design to help debug unknown events.
Cell Broadband Engine, debugging, unknown events, high-speed processors
Mack W. Riley, Mike Genden, "Cell Broadband Engine Debugging for Unknown Events", IEEE Design & Test of Computers, vol.24, no. 5, pp. 486-493, September-October 2007, doi:10.1109/MDT.2007.157
1. M. Riley et al., "Debug of the CELL Processor: Moving the Lab into Silicon," Proc. IEEE Int'l Test Conf. (ITC 06), IEEE CS Press, 2006, art. 297671 (9 pp.).
2. D. Pham et al., "The Design and Implementation of a First-Generation CELL Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 184–185, 592.
3. B. Flachs et al., "A Streaming Processor Unit for a CELL Processor," Proc. IEEE Int'l Solid-State Circuits Conf. (ISSCC 05), IEEE Press, 2005, pp. 134–135.
4. M. Levitt, "Designing UltraSparc for Testability," IEEE Design &Test, vol. 14, no. 1, Jan.-Mar. 1997, pp. 10–17.
5. A. Crouch, M. Pressly, and J. Circello, "Testability Features of the MC69060 Microprocessor," Proc. Int'l Test Conf. (ITC 94), IEEE CS Press, 1994, pp. 60–69.
6. D. Josephson, D. Dixon, and B. Arnold, "Test Features of the HP PA7100LC Processor," Proc. Int'l Test Conf. (ITC 93), IEEE CS Press, 1993, pp. 764–772.
101 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool