Mar. 25, 2009 to Mar. 27, 2009
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/UKSIM.2009.30
In the present paper, we present the designand implementation of a 64-bit reduced instruction set(RISC) processor with built-in-self test (BIST) features. Abuilt-in self-test (BIST) or built-in test (BIT) is amechanism that permits a machine to test itself. Keyfeatures of the design including its architecture, datapath, and instruction set are presented. The design isimplemented using VHDL and verified on Xilinx ISEsimulator. The processor is designed keeping in mindspecific applications. The proposed design may findapplications where automation and control is required.Illustrations highlight the typical use of our processor inbottling plants and control of robotic movements usingexhaustive simulations. Future applications may includeits use in vending machines, ATMs, mobile phones, andportable gaming kits.
RISC, BIST, BIT, VHDL
Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin, Pranav Bhasker, Ishita Verma, "Design and Implementation of a 64-bit RISC Processor Using VHDL", UKSIM, 2009, Computer Modeling and Simulation, International Conference on, Computer Modeling and Simulation, International Conference on 2009, pp. 568-573, doi:10.1109/UKSIM.2009.30