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Microarchitectural dI/dt Control
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1198684May/June 2003 (vol. 20 no. 3) pp. 40-47
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Ed Grochowski, David Ayers, Vivek Tiwari, "Microarchitectural dI/dt Control," IEEE Design and Test of Computers, vol. 20, no. 3, pp. 40-47, May/June, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1198684,
author = {Ed Grochowski and David Ayers and Vivek Tiwari},
title = {Microarchitectural dI/dt Control},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {3},
issn = {0740-7475},
year = {2003},
pages = {40-47},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1198684},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Design and Test of Computers
TI - Microarchitectural dI/dt Control
IS - 3
SN - 0740-7475
SP40
EP47
EPD - 40-47
A1 - Ed Grochowski,
A1 - David Ayers,
A1 - Vivek Tiwari,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
David Ayers, Intel
Vivek Tiwari, Intel

Editor?s note:

This article takes a high-level view of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through an astonishing set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation, giving insight into possible methods to reduce such noise.
--Sani R. Nassif, IBM Austin Research Laboratory

Citation:
Ed Grochowski, David Ayers, Vivek Tiwari, "Microarchitectural dI/dt Control," IEEE Design and Test of Computers, vol. 20, no. 3, pp. 40-47, May/June 2003, doi:10.1109/MDT.2003.1198684
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