loading...
Compacting Test Responses for Deeply Embedded SoC Cores
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1214349July/August 2003 (vol. 20 no. 4) pp. 22-30
 This Article 
 
PDF
HTML
 
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Ozgur Sinanoglu, University of California, San Diego
Alex Orailoglu, University of California, San Diego

Test bandwidth allocation issues greatly limit parallel testing of SoC cores. Here, the authors propose a response compaction methodology for reducing the required output core bandwidth, enabling increased parallelism among core tests and hence reducing overall SoC test time.

Citation:
Ozgur Sinanoglu, Alex Orailoglu, "Compacting Test Responses for Deeply Embedded SoC Cores," IEEE Design and Test of Computers, vol. 20, no. 4, pp. 22-30, July/Aug. 2003, doi:10.1109/MDT.2003.1214349
Usage of this product signifies your acceptance of the Terms of Use.