High-Frequency, At-Speed Scan Testing

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http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232252

September/October 2003 (vol. 20 no. 5) pp. 17-25

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	Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli, "High-Frequency, At-Speed Scan Testing," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 17-25, September/October, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1232252, author = {Xijiang Lin and Ron Press and Janusz Rajski and Paul Reuter and Thomas Rinderknecht and Bruce Swanson and Nagesh Tamarapalli}, title = {High-Frequency, At-Speed Scan Testing}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {5}, issn = {0740-7475}, year = {2003}, pages = {17-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232252}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - High-Frequency, At-Speed Scan Testing IS - 5 SN - 0740-7475 SP17 EP25 EPD - 17-25 A1 - Xijiang Lin, A1 - Ron Press, A1 - Janusz Rajski, A1 - Paul Reuter, A1 - Thomas Rinderknecht, A1 - Bruce Swanson, A1 - Nagesh Tamarapalli, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Xijiang Lin, Mentor Graphics

Ron Press, Mentor Graphics

Janusz Rajski, Mentor Graphics

Paul Reuter, Mentor Graphics

Thomas Rinderknecht, Mentor Graphics

Bruce Swanson, Mentor Graphics

Nagesh Tamarapalli, Mentor Graphics

Editor's note:

At-speed scan testing has demonstrated many successes in industry. One key feature is its ability to use on-chip clock for accurate timing in the application of test vectors in a tester. The authors describe new strategies where at-speed scan tests can be applied with internal PLLs. They present techniques for optimizing ATPG across multiple clock domains and propose methodologies to combine both stuck-at-fault and delay-test vectors into an effective test suite.

—Li-C. Wang, University of California, Santa Barbara

Citation:

Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli, "High-Frequency, At-Speed Scan Testing," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 17-25, Sep./Oct. 2003, doi:10.1109/MDT.2003.1232252

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