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Speed Binning with Path Delay Test in 150-nm Technology
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232255September/October 2003 (vol. 20 no. 5) pp. 41-45
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Bruce D. Cory, Rohit Kapur, Bill Underwood, "Speed Binning with Path Delay Test in 150-nm Technology," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 41-45, September/October, 2003.
 
 
BibTex
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@article{ 10.1109/MDT.2003.1232255,
author = {Bruce D. Cory and Rohit Kapur and Bill Underwood},
title = {Speed Binning with Path Delay Test in 150-nm Technology},
journal ={IEEE Design and Test of Computers},
volume = {20},
number = {5},
issn = {0740-7475},
year = {2003},
pages = {41-45},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232255},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Speed Binning with Path Delay Test in 150-nm Technology
IS - 5
SN - 0740-7475
SP41
EP45
EPD - 41-45
A1 - Bruce D. Cory,
A1 - Rohit Kapur,
A1 - Bill Underwood,
PY - 2003
VL - 20
JA - IEEE Design and Test of Computers
ER -
 
Bruce D. Cory, nVidia
Rohit Kapur, Synopsys
Bill Underwood, Synopsys

Editor's note:
What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system-operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.
—Li-C. Wang, University of California, Santa Barbara

Citation:
Bruce D. Cory, Rohit Kapur, Bill Underwood, "Speed Binning with Path Delay Test in 150-nm Technology," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 41-45, Sep./Oct. 2003, doi:10.1109/MDT.2003.1232255
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