An On-Chip Self-Repair Calculation and Fusing Methodology

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http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232258

September/October 2003 (vol. 20 no. 5) pp. 67-75

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	ASCII Text	x
	Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steve Oakland, Michael R. Ouellette, Donald L. Wheater, "An On-Chip Self-Repair Calculation and Fusing Methodology," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 67-75, September/October, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1232258, author = {Darren Anand and Bruce Cowan and Owen Farnsworth and Peter Jakobsen and Steve Oakland and Michael R. Ouellette and Donald L. Wheater}, title = {An On-Chip Self-Repair Calculation and Fusing Methodology}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {5}, issn = {0740-7475}, year = {2003}, pages = {67-75}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1232258}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - An On-Chip Self-Repair Calculation and Fusing Methodology IS - 5 SN - 0740-7475 SP67 EP75 EPD - 67-75 A1 - Darren Anand, A1 - Bruce Cowan, A1 - Owen Farnsworth, A1 - Peter Jakobsen, A1 - Steve Oakland, A1 - Michael R. Ouellette, A1 - Donald L. Wheater, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Darren Anand, IBM

Bruce Cowan, IBM

Owen Farnsworth, IBM

Peter Jakobsen, IBM

Steve Oakland, IBM

Michael R. Ouellette, IBM

Donald L. Wheater, IBM

Editor's note:

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

—Rob Aitken, Artisan Components

Citation:

Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steve Oakland, Michael R. Ouellette, Donald L. Wheater, "An On-Chip Self-Repair Calculation and Fusing Methodology," IEEE Design and Test of Computers, vol. 20, no. 5, pp. 67-75, Sep./Oct. 2003, doi:10.1109/MDT.2003.1232258

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