Design and Characterization of Null Convention Self-Timed Multipliers

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http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246161

November/December 2003 (vol. 20 no. 6) pp. 26-36

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	Satish K. Bandapati, Scott C. Smith, Minsu Choi, "Design and Characterization of Null Convention Self-Timed Multipliers," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 26-36, November/December, 2003.

	BibTex	x
	@article{ 10.1109/MDT.2003.1246161, author = {Satish K. Bandapati and Scott C. Smith and Minsu Choi}, title = {Design and Characterization of Null Convention Self-Timed Multipliers}, journal ={IEEE Design and Test of Computers}, volume = {20}, number = {6}, issn = {0740-7475}, year = {2003}, pages = {26-36}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1246161}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Design and Characterization of Null Convention Self-Timed Multipliers IS - 6 SN - 0740-7475 SP26 EP36 EPD - 26-36 A1 - Satish K. Bandapati, A1 - Scott C. Smith, A1 - Minsu Choi, PY - 2003 VL - 20 JA - IEEE Design and Test of Computers ER -

Satish K. Bandapati, University of Missouri-Rolla

Scott C. Smith, University of Missouri-Rolla

Minsu Choi, University of Missouri-Rolla

Editor's note: This article presents various 4-bit × 4-bit unsigned multipliers designed using the delay-insensitive null convention logic paradigm. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study will serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.

—Yong-Bin Kim, Northeastern University

Citation:

Satish K. Bandapati, Scott C. Smith, Minsu Choi, "Design and Characterization of Null Convention Self-Timed Multipliers," IEEE Design and Test of Computers, vol. 20, no. 6, pp. 26-36, Nov./Dec. 2003, doi:10.1109/MDT.2003.1246161

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