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Hierarchical Modeling of the VLSI Design Process
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/64.79710April 1991 (vol. 6 no. 2) pp. 56-70
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Amir K. Hekmatpour, Alex Orailoglu, Paul Chau, "Hierarchical Modeling of the VLSI Design Process," IEEE Intelligent Systems, vol. 6, no. 2, pp. 56-70, April, 1991.
 
 
BibTex
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@article{ 10.1109/64.79710,
author = {Amir K. Hekmatpour and Alex Orailoglu and Paul Chau},
title = {Hierarchical Modeling of the VLSI Design Process},
journal ={IEEE Intelligent Systems},
volume = {6},
number = {2},
issn = {0885-9000},
year = {1991},
pages = {56-70},
doi = {http://doi.ieeecomputersociety.org/10.1109/64.79710},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Intelligent Systems
TI - Hierarchical Modeling of the VLSI Design Process
IS - 2
SN - 0885-9000
SP56
EP70
EPD - 56-70
A1 - Amir K. Hekmatpour,
A1 - Alex Orailoglu,
A1 - Paul Chau,
PY - 1991
VL - 6
JA - IEEE Intelligent Systems
ER -
 

A description is given of the Kinden environment, which combines object-oriented modeling and model-based reasoning to capture, integrate, and manage VLSI design process attributes and hierarchies. Related work is briefly reviewed, and the modeling of the design process is discussed, focusing on the Kinden approach. The model-based reasoning on which Kinden's knowledge-processing architecture is based is described. The present implementation of Kinden is examined.

Citation:
Amir K. Hekmatpour, Alex Orailoglu, Paul Chau, "Hierarchical Modeling of the VLSI Design Process," IEEE Intelligent Systems, vol. 6, no. 2, pp. 56-70, Apr. 1991, doi:10.1109/64.79710
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