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An Interconnect Architecture for Networking Systems on Chips
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044298September/October 2002 (vol. 22 no. 5) pp. 36-45
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Faraydon Karim, Anh Nguyen, Sujit Dey, "An Interconnect Architecture for Networking Systems on Chips," IEEE Micro, vol. 22, no. 5, pp. 36-45, September/October, 2002.
 
 
BibTex
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@article{ 10.1109/MM.2002.1044298,
author = {Faraydon Karim and Anh Nguyen and Sujit Dey},
title = {An Interconnect Architecture for Networking Systems on Chips},
journal ={IEEE Micro},
volume = {22},
number = {5},
issn = {0272-1732},
year = {2002},
pages = {36-45},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044298},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Micro
TI - An Interconnect Architecture for Networking Systems on Chips
IS - 5
SN - 0272-1732
SP36
EP45
EPD - 36-45
A1 - Faraydon Karim,
A1 - Anh Nguyen,
A1 - Sujit Dey,
PY - 2002
VL - 22
JA - IEEE Micro
ER -
 

Network processor systems on chips meet the speed and flexibility requirements of next-generation internet routers. The octagon on-chip communication architecture, with its cost, performance, and scalability advantages, supports these network processor SOCs.

Citation:
Faraydon Karim, Anh Nguyen, Sujit Dey, "An Interconnect Architecture for Networking Systems on Chips," IEEE Micro, vol. 22, no. 5, pp. 36-45, Sep./Oct. 2002, doi:10.1109/MM.2002.1044298
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