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SOI Technology for Future High-Performance Smart Cards
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2003.1209467May/June 2003 (vol. 23 no. 3) pp. 58-67
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Amaury N?ve, Denis Flandre, Jean-Jacques Quisquater, "SOI Technology for Future High-Performance Smart Cards," IEEE Micro, vol. 23, no. 3, pp. 58-67, May/June, 2003.
 
 
BibTex
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@article{ 10.1109/MM.2003.1209467,
author = {Amaury N?ve and Denis Flandre and Jean-Jacques Quisquater},
title = {SOI Technology for Future High-Performance Smart Cards},
journal ={IEEE Micro},
volume = {23},
number = {3},
issn = {0272-1732},
year = {2003},
pages = {58-67},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1209467},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Micro
TI - SOI Technology for Future High-Performance Smart Cards
IS - 3
SN - 0272-1732
SP58
EP67
EPD - 58-67
A1 - Amaury N?ve,
A1 - Denis Flandre,
A1 - Jean-Jacques Quisquater,
PY - 2003
VL - 23
JA - IEEE Micro
ER -
 
Amaury N?ve, Universit? catholique de Louvain
Denis Flandre, Universit? catholique de Louvain
Jean-Jacques Quisquater, Universit? catholique de Louvain

Chips based on silicon-on-insulator technology meet the tough performance and security requirements presented by smart cards. A test chip manufactured in a fully depleted SOI process incorporates a charge pump and random-number generator, critical smart-card circuit blocks.

Citation:
Amaury N?ve, Denis Flandre, Jean-Jacques Quisquater, "SOI Technology for Future High-Performance Smart Cards," IEEE Micro, vol. 23, no. 3, pp. 58-67, May/June 2003, doi:10.1109/MM.2003.1209467
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