Asynchronous Interconnect for Synchronous SoC Design

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http://doi.ieeecomputersociety.org/10.1109/MM.2004.1268991

January/February 2004 (vol. 24 no. 1) pp. 32-41

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	ASCII Text	x
	Andrew Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, pp. 32-41, January/February, 2004.

	BibTex	x
	@article{ 10.1109/MM.2004.1268991, author = {Andrew Lines}, title = {Asynchronous Interconnect for Synchronous SoC Design}, journal ={IEEE Micro}, volume = {24}, number = {1}, issn = {0272-1732}, year = {2004}, pages = {32-41}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.1268991}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Asynchronous Interconnect for Synchronous SoC Design IS - 1 SN - 0272-1732 SP32 EP41 EPD - 32-41 A1 - Andrew Lines, PY - 2004 VL - 24 JA - IEEE Micro ER -

Andrew Lines, Fulcrum Microsystems

Asynchronous circuits can efficiently interconnect system-on-chip modules with different clock domains. Fulcrum's Nexus Interconnect features a 16-port, 36-bit asynchronous crossbar that connects through asynchronous channels to clock-domain converters for each synchronous module. In TSMC'S 130-nm process, Nexus achieves 1.35 GHz and transfers 780 Gbps.

Citation:

Andrew Lines, "Asynchronous Interconnect for Synchronous SoC Design," IEEE Micro, vol. 24, no. 1, pp. 32-41, Jan./Feb. 2004, doi:10.1109/MM.2004.1268991

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