The vector-thread (VT) architecture supports a seamless intermingling of vector and multithreaded computation to flexibly and compactly encode application parallelism and locality. VT processors exploit this encoding to provide high performance with low power and small area.
Citation:
Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic, "The Vector-Thread Architecture," IEEE Micro, vol. 24, no. 6, pp. 84-90, Nov./Dec. 2004, doi:10.1109/MM.2004.90