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Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation
Newcastle upon Tyne, UK June 25-June 29
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CSD.2001.981774Second International Conference on Ap ...
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O. Garnica, Universidad Complutense de Madrid
J. Lanchares, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
This paper is devoted to studying two key issues of the asynchronous pipelines: their performance, and the influence that the position of stages have on the latency of a pipelined asynchronous circuit as a whole. To attain the performance evaluation, we derive expressions of the latency and the cycle time of a linear pipeline as closed-form formulas. To attain the influence of the position, we present some experiments, using the previous closed-form formulas, on different pipelines.
Citation:
O. Garnica, J. Lanchares, R. Hermida, "Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation," acsd, pp.167, Second International Conference on Application of Concurrency to System Design (ACSD'01), 2001
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