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Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition
Adelaide, Australia April 14-April 16
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.1999.76282414th IEEE Symposium on Computer Arith ...
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Dhananjay S. Phatak, State University of New York at Binghamton
I. Koren, University of Massachusetts
In two operand addition, bit-wise intermediate variables such as the "propagate" and "generate" terms are defined/ evaluated first. Basic carry propagation recursion is then expressed in terms of these variables and is "unrolled" to obtain a tree structure for fast execution. In CMOS VLSI technology, multiplexors are fast and efficient to implement. Hence, we investigate in this paper all possible two-bit encodings for the intermediate variables and identify the ones that enable multiplexor-based implementations. Some of these encodings enable further simplification of the multiplexor-based realizations. Our analysis also shows that adopting an intermediate signed-digit representation simply amounts to selecting one of the possible encodings. Thus, there is no inherent advantage to the use of intermediate signed-digit representations in a two operand addition. Finally, we extend our analysis to the generalized look-ahead-recursions proposed by Doran.
Citation:
Dhananjay S. Phatak, I. Koren, "Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition," arith, pp.22, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99), 1999
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