Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow

Adelaide, Australia April 14-April 16

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ARITH.1999.762853

14th IEEE Symposium on Computer Arith ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Guenter Gerwig Articles by Michael Kroener

	ASCII Text	x
	Guenter Gerwig, Michael Kroener, "Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow," Computer Arithmetic, IEEE Symposium on, pp. 266, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99), 1999.

	BibTex	x
	@article{ 10.1109/ARITH.1999.762853, author = {Guenter Gerwig and Michael Kroener}, title = {Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {1999}, issn = {1063-6889}, pages = {266}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.1999.762853}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow SN - 1063-6889 SP EP A1 - Guenter Gerwig, A1 - Michael Kroener, PY - 1999 VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER -

Guenter Gerwig, IBM

Michael Kroener, IBM

The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the register array, there are no other dataflow macros used; it is fully designed with standard cell books and is placed flat with a timing driven placement algorithm. This design method allows more 'irregular' structures than usually found in custom designs.An overview of the floating-point unit is given and some interesting design items are shown: a 120 bit-wide true-complement adder with precounting of leading zero digits, a signed multiplier with bit-optimized Wallace tree, intensive forwarding in source equal target cases and the checking method.

Citation:

Guenter Gerwig, Michael Kroener, "Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow," arith, pp.266, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 '99), 1999

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.