High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands

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http://doi.ieeecomputersociety.org/10.1109/ARITH.2001.930121

15th IEEE Symposium on Computer Arith ...

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	H.T. Vergos, D. Nikolos, C. Efstathiou, "High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands," Computer Arithmetic, IEEE Symposium on, pp. 0211, 15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01), 2001.

	BibTex	x
	@article{ 10.1109/ARITH.2001.930121, author = {H.T. Vergos and D. Nikolos and C. Efstathiou}, title = {High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands}, journal ={Computer Arithmetic, IEEE Symposium on}, volume = {0}, year = {2001}, isbn = {0-7695-1150-3}, pages = {0211}, doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2001.930121}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Arithmetic, IEEE Symposium on TI - High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands SN - 0-7695-1150-3 SP EP A1 - H.T. Vergos, A1 - D. Nikolos, A1 - C. Efstathiou, PY - 2001 VL - 0 JA - Computer Arithmetic, IEEE Symposium on ER -

H.T. Vergos, University of Patras

D. Nikolos, University of Patras

C. Efstathiou, TEI of Athens

Abstract: We present a new methodology for designing modulo 2n +1 adders with operands in the diminished-one number system. The proposed methodology leads to parallel-prefix adder implementations. Both an analytical model and VLSI implementations in a standard-cell technology are utilized for comparing the adders designed following the proposed methodology against the existing solutions. Our results indicate that the proposed parallel-prefix adders are considerably faster than any other already known in the open literature and as fast as the corresponding modulo 2 n and modulo 2n-1 adders.

Citation:

H.T. Vergos, D. Nikolos, C. Efstathiou, "High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands," arith, pp.0211, 15th IEEE Symposium on Computer Arithmetic (ARITH-15 '01), 2001

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