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A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm
Santiago de Compostela, Spain June 15-June 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.120766016th IEEE Symposium on Computer Arith ...
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Eric Rice, University of California at Santa Cruz
Richard Hughey, University of California at Santa Cruz
This paper presents a new approach to hardware division— the parallel paths algorithm. In this approach, prescaling allows the division recurrence to be implemented by three processes which can be calculated in parallel during iterations. While two of the processes must complete in a single iteration, the third — which includes the most expensive division operations — can be calculated over multiple iterations. Iteration latency is determined by the slowest of the three paths, and in many cases can be limited to that of carry-save addition and latching. A radix-4 implementation of the algorithmis shown to achieve better performance than other commonly used methods while requiring a modest increase in area.
Index Terms:
Computer arithmetic, hardware division, prescaling, linear convergence
Citation:
Eric Rice, Richard Hughey, "A New Iterative Structure for Hardware Division: The Parallel Paths Algorithm," arith, pp.54, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003
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