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Saturating Counters: Application and Design Alternatives
Santiago de Compostela, Spain June 15-June 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.120768316th IEEE Symposium on Computer Arith ...
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Israel Koren, University of Massachusetts at Amherst
Yaron Koren, Bear Stearns
Bejoy G. Oomman, Genesys Testware
We define a new class of parallel counters, Saturating Counters, which provide the exact count of the inputs that are 1 only if this count is below a given threshold. Such counters are useful in, for example, a self-test and repair unit for embedded memories in a system-on-a-chip. We describe this application and present several alternatives for the design of the saturating counter. We then compare the delay and area of the proposed design alternatives.
Citation:
Israel Koren, Yaron Koren, Bejoy G. Oomman, "Saturating Counters: Application and Design Alternatives," arith, pp.228, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003
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