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Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders
Santiago de Compostela, Spain June 15-June 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.120768816th IEEE Symposium on Computer Arith ...
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Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, Ram Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders," Computer Arithmetic, IEEE Symposium on, pp. 272, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003.
 
 
BibTex
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@article{ 10.1109/ARITH.2003.1207688,
author = {Vojin G. Oklobdzija and Bart R. Zeydel and Hoang Dao and Sanu Mathew and Ram Krishnamurthy},
title = {Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders},
journal ={Computer Arithmetic, IEEE Symposium on},
volume = {0},
year = {2003},
issn = {1063-6889},
pages = {272},
doi = {http://doi.ieeecomputersociety.org/10.1109/ARITH.2003.1207688},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Computer Arithmetic, IEEE Symposium on
TI - Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders
SN - 1063-6889
SP
EP
A1 - Vojin G. Oklobdzija,
A1 - Bart R. Zeydel,
A1 - Hoang Dao,
A1 - Sanu Mathew,
A1 - Ram Krishnamurthy,
PY - 2003
KW - null
VL - 0
JA - Computer Arithmetic, IEEE Symposium on
ER -
 
Vojin G. Oklobdzija, University of California at Davis
Bart R. Zeydel, University of California at Davis
Hoang Dao, University of California at Davis
Sanu Mathew, Intel Corporation
Ram Krishnamurthy, Intel Corporation
In this paper, we motivate the concept of comparing VLSI adders based on their energy-delay trade-offs and present a technique for estimating the energy-delay space of various high-performance VLSI adder topologies. Further, we show that our estimates accurately represent tradeoffs in the energy-delay space for high-performance 32-bit and 64-bit processor adders in 0.13 ?m and 0.10 ?m CMOS technologies, with an accuracy of 8% in delay estimates and 20% in energy estimates, compared with simulated data.
Citation:
Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Dao, Sanu Mathew, Ram Krishnamurthy, "Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders," arith, pp.272, 16th IEEE Symposium on Computer Arithmetic (ARITH-16 '03), 2003
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