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Hardware Implementation of an Elliptic Curve Processor over GF(p)
The Hague, The Netherlands June 24-June 26
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.121286614th IEEE International Conference on ...
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S?dd?ka Berna Ors, Lejla Batina, Bart Preneel, Joos Vandewalle, "Hardware Implementation of an Elliptic Curve Processor over GF(p)," Application-Specific Systems, Architectures and Processors, IEEE International Conference on, pp. 433, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003.
 
 
BibTex
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@article{ 10.1109/ASAP.2003.1212866,
author = {S?dd?ka Berna Ors and Lejla Batina and Bart Preneel and Joos Vandewalle},
title = {Hardware Implementation of an Elliptic Curve Processor over GF(p)},
journal ={Application-Specific Systems, Architectures and Processors, IEEE International Conference on},
volume = {0},
year = {2003},
issn = {1063-6862},
pages = {433},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212866},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
TI - Hardware Implementation of an Elliptic Curve Processor over GF(p)
SN - 1063-6862
SP
EP
A1 - S?dd?ka Berna Ors,
A1 - Lejla Batina,
A1 - Bart Preneel,
A1 - Joos Vandewalle,
PY - 2003
KW - Elliptic Curve Cryptosystems
KW - Modular Operations
KW - FPGA
VL - 0
JA - Application-Specific Systems, Architectures and Processors, IEEE International Conference on
ER -
 
S?dd?ka Berna Ors, Katholieke Universiteit Leuven, ESAT/SCD-COSIC
Lejla Batina, SafeNet BV/Katholieke Universiteit Leuven, ESAT/SCD-COSIC
Bart Preneel, Katholieke Universiteit Leuven, ESAT/SCD-COSIC
Joos Vandewalle, Katholieke Universiteit Leuven, ESAT/SCD-COSIC
This paper describes a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography (PKC), i.e., Elliptic Curve (EC) and RSA Cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery Modular Multiplication, modular addition/subtraction, EC Point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.
Index Terms:
Elliptic Curve Cryptosystems, Modular Operations, FPGA
Citation:
S?dd?ka Berna Ors, Lejla Batina, Bart Preneel, Joos Vandewalle, "Hardware Implementation of an Elliptic Curve Processor over GF(p)," asap, pp.433, 14th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP'03), 2003
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