A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications

Wanchai, Hong Kong January 18-January 21

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http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759702

Asia and South Pacific Design Automat ...

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	ASCII Text	x
	Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon, "A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications," Asia and South Pacific Design Automation Conference, pp. 29, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASPDAC.1999.759702, author = {Byeong-Lyeol Jeon and Kang-Jin Lee and Seung-Hoon Lee and Sang-Won Yoon}, title = {A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications}, journal ={Asia and South Pacific Design Automation Conference}, volume = {0}, year = {1999}, isbn = {0-7803-5012-X}, pages = {29}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.1999.759702}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asia and South Pacific Design Automation Conference TI - A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications SN - 0-7803-5012-X SP EP A1 - Byeong-Lyeol Jeon, A1 - Kang-Jin Lee, A1 - Seung-Hoon Lee, A1 - Sang-Won Yoon, PY - 1999 KW - null VL - 0 JA - Asia and South Pacific Design Automation Conference ER -

Byeong-Lyeol Jeon, Sogang University, Seoul, Korea

Kang-Jin Lee, Hyundai Electronics Industries Co., Ltd., Ichon, Korea

Seung-Hoon Lee, Sogang University, Seoul, Korea

Sang-Won Yoon, Sogang University, Seoul, Korea

This paper describes a 10b 50 MHz CMOS ADC for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a power reduction technique for high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 um CMOS show less than ±0.6 LSB and ±2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz.

Citation:

Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon, "A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications," asp-dac, pp.29, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999

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