Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for two-layer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
Citation:
Maolin Tang, Kamran Eshraghian, Hon Nin Cheung, "An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing," asp-dac, pp.149, Asia and South Pacific Design Automation Conference 1999 (ASP-DAC'99), 1999