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High-level test evaluation of asynchronous circuits
London, England May 30-May 31
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514643Second Working Conference on Asynchro ...
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R. van de Wiel, Dept. of Math. & Comput. Sci., Eindhoven Univ. of Technol., Netherlands
The present a method for evaluating production fault tests for asynchronous circuits. A novel fault model is defined, based on a high-level circuit description, allowing the evaluation of production tests on the design level. This evaluation method is used in the test generation for an asynchronous 22 k transistor DCC error corrector IC, resulting in a fault coverage of 99.8%.
Index Terms:
asynchronous circuits; logic testing; VLSI; error detection codes; asynchronous circuits; high-level test evaluation; production fault tests; fault model; high-level circuit description; asynchronous 22 k transistor DCC error corrector IC
Citation:
R. van de Wiel, "High-level test evaluation of asynchronous circuits," async, pp.63, Second Working Conference on Asynchronous Design Methodologies, 1995
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