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Asynchronous circuits based on multiple localised current-sensing completion detection
London, England May 30-May 31
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514654Second Working Conference on Asynchro ...
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E. Grass, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
S. Jones, Dept. of Electron. & Electr. Eng., Loughborough Univ. of Technol., UK
Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC's) which fully support the advantages of CSCD are presented. Multiple localised CSC's are studied and an example of a 4-bit parallel multiplier is investigated on different levels of granularity.
Index Terms:
asynchronous circuits; logic design; power consumption; asynchronous circuits; dual rail coding; Current-Sensing Completion Detection; parallel multiplier; granularity; Current-Sensing Circuits; BiCMOS
Citation:
E. Grass, S. Jones, "Asynchronous circuits based on multiple localised current-sensing completion detection," async, pp.170, Second Working Conference on Asynchronous Design Methodologies, 1995
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