ECSTAC: a fast asynchronous microprocessor

London, England May 30-May 31

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http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514655

Second Working Conference on Asynchro ...

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	ASCII Text	x
	S.V. Morton, S.S. Appleton, M.J. Liebelt, "ECSTAC: a fast asynchronous microprocessor," Asynchronous Circuits and Systems, International Symposium on, pp. 180, Second Working Conference on Asynchronous Design Methodologies, 1995.

	BibTex	x
	@article{ 10.1109/WCADM.1995.514655, author = {S.V. Morton and S.S. Appleton and M.J. Liebelt}, title = {ECSTAC: a fast asynchronous microprocessor}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1995}, isbn = {0-8186-7098-3}, pages = {180}, doi = {http://doi.ieeecomputersociety.org/10.1109/WCADM.1995.514655}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - ECSTAC: a fast asynchronous microprocessor SN - 0-8186-7098-3 SP EP A1 - S.V. Morton, A1 - S.S. Appleton, A1 - M.J. Liebelt, PY - 1995 KW - asynchronous circuits; microprocessor chips; logic design; asynchronous microprocessor; ECSTAC; two-phase communication; processor pipeline; register tagging; branch techniques; caches; block simulation VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

S.V. Morton, Southbank Univ., London, UK

S.S. Appleton, Southbank Univ., London, UK

M.J. Liebelt, Southbank Univ., London, UK

This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given.

Index Terms:

asynchronous circuits; microprocessor chips; logic design; asynchronous microprocessor; ECSTAC; two-phase communication; processor pipeline; register tagging; branch techniques; caches; block simulation

Citation:

S.V. Morton, S.S. Appleton, M.J. Liebelt, "ECSTAC: a fast asynchronous microprocessor," async, pp.180, Second Working Conference on Asynchronous Design Methodologies, 1995

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