Timed Trace Theoretic Verification Using Partial Order Reduction

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http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761527

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	ASCII Text	x
	Tomohiro Yoneda, Hiroshi Ryu, "Timed Trace Theoretic Verification Using Partial Order Reduction," Asynchronous Circuits and Systems, International Symposium on, pp. 108, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999.

	BibTex	x
	@article{ 10.1109/ASYNC.1999.761527, author = {Tomohiro Yoneda and Hiroshi Ryu}, title = {Timed Trace Theoretic Verification Using Partial Order Reduction}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {1999}, issn = {1522-8681}, pages = {108}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.1999.761527}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - Timed Trace Theoretic Verification Using Partial Order Reduction SN - 1522-8681 SP EP A1 - Tomohiro Yoneda, A1 - Hiroshi Ryu, PY - 1999 VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Tomohiro Yoneda, Tokyo Institute of Technology

Hiroshi Ryu, NEC Corporation

In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.

Citation:

Tomohiro Yoneda, Hiroshi Ryu, "Timed Trace Theoretic Verification Using Partial Order Reduction," async, pp.108, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC'99), 1999

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