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Clock Synchronization through Handshake Signalling
Manchester, United Kingdom April 08-April 11
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASYNC.2002.10002Eighth International Symposium on Asy ...
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Joep Kessels, Philips Research
Suk-Jin Kim, Kwang-Ju Institute of Science and Technology
Ad Peeters, Philips Research
Paul Wielage, Philips Research

We present a method for synchronizing pausible clocks in GALS (Globally Asynchronous, Locally Synchronous) systems. In contrast to most conventional GALS schemes the method is not based on including in each ring oscillator a synchronizing element (such as for instance an arbiter) which on one side can pause the clock and on the other side offers a handshake interface. Instead, we propose a scheme in which each synchronous module has both an incoming and an outgoing clock signal, which have been obtained by opening the module's ring oscillator. Since these clock signals also behave as handshake signals, handshake circuits can be used to synchronize the clocks.

We demonstrate the technique in the context of processors and memories. All the designs have been simulated and showed functionally correct.

Index Terms:
GALS systems, pausible clocks, asynchronous crossbar/bus, processor/memory architectures
Citation:
Joep Kessels, Suk-Jin Kim, Ad Peeters, Paul Wielage, "Clock Synchronization through Handshake Signalling," async, pp.59, Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC'02), 2002
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