SNAP: A Sensor-Network Asynchronous Processor

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http://doi.ieeecomputersociety.org/10.1109/ASYNC.2003.1199163

Ninth IEEE International Symposium on ...

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	Clinton Kelly, IV, Virantha Ekanayake, Rajit Manohar, "SNAP: A Sensor-Network Asynchronous Processor," Asynchronous Circuits and Systems, International Symposium on, pp. 24, Ninth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03), 2003.

	BibTex	x
	@article{ 10.1109/ASYNC.2003.1199163, author = {Clinton Kelly, IV and Virantha Ekanayake and Rajit Manohar}, title = {SNAP: A Sensor-Network Asynchronous Processor}, journal ={Asynchronous Circuits and Systems, International Symposium on}, volume = {0}, year = {2003}, issn = {1522-8681}, pages = {24}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2003.1199163}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asynchronous Circuits and Systems, International Symposium on TI - SNAP: A Sensor-Network Asynchronous Processor SN - 1522-8681 SP EP A1 - Clinton Kelly, IV, A1 - Virantha Ekanayake, A1 - Rajit Manohar, PY - 2003 KW - null VL - 0 JA - Asynchronous Circuits and Systems, International Symposium on ER -

Clinton Kelly, IV, Cornell University

Virantha Ekanayake, Cornell University

Rajit Manohar, Cornell University

We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, the Network on a Chip (NoC), which will execute a novel sensor-network simulator. We discuss the advantages of using the same processor for nodes in physical and simulated sensor networks. We describe the attributes that a processor must possess to function well in both roles, and we then describe the way we designed SNAP to have these attributes.

Citation:

Clinton Kelly, IV, Virantha Ekanayake, Rajit Manohar, "SNAP: A Sensor-Network Asynchronous Processor," async, pp.24, Ninth IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'03), 2003

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