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Transistor leakage fault location with ZDDQ measurement
Bangalore, India November 23-November 24
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485316Fourth Asian Test Symposium (ATS'95)
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Wen Xiaoqing, Min. Coll., Akita Univ., Japan
H. Tamamoto, Min. Coll., Akita Univ., Japan
K. Kinoshita, Min. Coll., Akita Univ., Japan
This paper discusses the problem of locating transistor leakage faults with only I/sub DDQ/ measurement. A new approach of equivalence fault collapsing is proposed for reducing the number of faults that must be considered. Fault location is performed by using both random and deterministic tests in order to obtain a high diagnostic resolution with a small number of tests. The experimental results show that the diagnosed faults are confined to only a few gates in many cases and that a very high average diagnostic resolution can be achieved for a gate-array circuit.
Index Terms:
fault location; fault diagnosis; logic testing; logic arrays; electric current measurement; leakage currents; CMOS logic circuits; field effect transistor circuits; transistor leakage fault location; I/sub DDQ/ measurement; equivalence fault collapsing; deterministic tests; random tests; diagnostic resolution; diagnosed faults; gate-array circuit; CMOS circuit
Citation:
Wen Xiaoqing, H. Tamamoto, K. Kinoshita, "Transistor leakage fault location with ZDDQ measurement," ats, pp.51, Fourth Asian Test Symposium (ATS'95), 1995
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