This paper presents an advanced concurrent simulation technique for performing Multiple Stuck-at Fault Simulation based on Multiple Domain Concurrent and Comparative Simulation (MDCCS). It efficiently compresses multiple experiments in a single simulation and requires no pre-analysis of the circuit. In addition, MDCCS has a unique feature that allows experiments to interact with each other and spawn offspring experiments should new behaviors arise. MDCCS is based on discrete event concurrent simulation (CS) and gains efficiency by utilizing the similarity among experiments without resorting to parallel hardware. It provides a mechanism for managing the complexity of interactions such that the implementation of this methodology is both storage and CPU time efficient. The intention of this paper is to present the MDCCS framework and report on its effectiveness for digital logic fault simulation.
Index Terms:
fault diagnosis; logic testing; circuit analysis computing; discrete event simulation; concurrent engineering; fault location; multiple stuck-at fault simulation; multiple domain simulation; comparative simulation; MDCCS; discrete event concurrent simulation; CPU time efficiency; digital logic fault simulation
Citation:
K.P. Lentz, E.S. Manolakos, E.C. Czeck, "On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative Simulation," ats, pp.86, Fourth Asian Test Symposium (ATS'95), 1995
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb