Invalid State Identification for Sequential Circuit Test Generation

Hsinchu, TAIWAN November 20-November 22

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http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555128

Fifth Asian Test Symposium (ATS'96)

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	Hsing-Chung Liang, Chung Len Lee, Jwu E Chen, "Invalid State Identification for Sequential Circuit Test Generation," Asian Test Symposium, pp. 10, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555128, author = {Hsing-Chung Liang and Chung Len Lee and Jwu E Chen}, title = {Invalid State Identification for Sequential Circuit Test Generation}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {10}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555128}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Invalid State Identification for Sequential Circuit Test Generation SN - 1081-7735 SP EP A1 - Hsing-Chung Liang, A1 - Chung Len Lee, A1 - Jwu E Chen, PY - 1996 KW - sequential circuits KW - invalid states KW - test generation VL - 0 JA - Asian Test Symposium ER -

Hsing-Chung Liang, National Chiao Tung University

Chung Len Lee, National Chiao Tung University

Jwu E Chen, National Chiao Tung University

For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation in the fault coverage, detection efficiency, and generation time.

Index Terms:

sequential circuits, invalid states, test generation

Citation:

Hsing-Chung Liang, Chung Len Lee, Jwu E Chen, "Invalid State Identification for Sequential Circuit Test Generation," ats, pp.10, Fifth Asian Test Symposium (ATS'96), 1996

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