Syndrome Simulation And Syndrome Test For Unscanned Interconnects

Hsinchu, TAIWAN November 20-November 22

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555138

Fifth Asian Test Symposium (ATS'96)

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Chauchin Su Articles by Shyh-Shen Hwang Articles by Shyh-Jye Jou Articles by Yuan-Tzu Ting

	ASCII Text	x
	Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting, "Syndrome Simulation And Syndrome Test For Unscanned Interconnects," Asian Test Symposium, pp. 62, Fifth Asian Test Symposium (ATS'96), 1996.

	BibTex	x
	@article{ 10.1109/ATS.1996.555138, author = {Chauchin Su and Shyh-Shen Hwang and Shyh-Jye Jou and Yuan-Tzu Ting}, title = {Syndrome Simulation And Syndrome Test For Unscanned Interconnects}, journal ={Asian Test Symposium}, volume = {0}, year = {1996}, issn = {1081-7735}, pages = {62}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555138}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Syndrome Simulation And Syndrome Test For Unscanned Interconnects SN - 1081-7735 SP EP A1 - Chauchin Su, A1 - Shyh-Shen Hwang, A1 - Shyh-Jye Jou, A1 - Yuan-Tzu Ting, PY - 1996 KW - boundary scan testing; unscanned interconnects; syndrome test methodology; event driven syndrome simulation; boundary scan environment; test length; faulty syndromes; fault-free syndromes; simulation algorithm; test cost reduction; set covering problem; tolerable error rate; partially scanned PCB; MCM; test pattern generation; weighted random patterns; board level testing VL - 0 JA - Asian Test Symposium ER -

Chauchin Su, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Shyh-Shen Hwang, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Shyh-Jye Jou, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Yuan-Tzu Ting, Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

In this paper, we present a syndrome test methodology for the testing of unscanned interconnects in a boundary scan environment. Mathematical equations are derived for the relationship of test length, fault-free and faulty syndromes, and tolerable error rate. To calculate fault-free and faulty syndromes, we propose an event driven syndrome simulation algorithm. To shorten testing time and reduce test cost, we transform and solve the problem as a set covering problem.

Index Terms:

boundary scan testing; unscanned interconnects; syndrome test methodology; event driven syndrome simulation; boundary scan environment; test length; faulty syndromes; fault-free syndromes; simulation algorithm; test cost reduction; set covering problem; tolerable error rate; partially scanned PCB; MCM; test pattern generation; weighted random patterns; board level testing

Citation:

Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting, "Syndrome Simulation And Syndrome Test For Unscanned Interconnects," ats, pp.62, Fifth Asian Test Symposium (ATS'96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.