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Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL
Akita, JAPAN November 17-November 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643908Sixth Asian Test Symposium (ATS'97)
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Tsuyoshi Shinogi, Faculty of Engineering, Mie University
Terumine Hayashi, Faculty of Engineering, Mie University
Kazuo Taki, Faculty of Engineering, Kobe University
This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem, we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.
Index Terms:
test generation, stuck-on fault, DFT circuit, pass-transistor logic
Citation:
Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki, "Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL," ats, pp.16, Sixth Asian Test Symposium (ATS'97), 1997
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