Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data

Akita, JAPAN November 17-November 18

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http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643953

Sixth Asian Test Symposium (ATS'97)

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	ASCII Text	x
	Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka, "Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data," Asian Test Symposium, pp. 162, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643953, author = {Katsuyoshi Miura and Kohei Nakata and Koji Nakamae and Hiromu Fujioka}, title = {Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {162}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643953}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data SN - 1081-7735 SP EP A1 - Katsuyoshi Miura, A1 - Kohei Nakata, A1 - Koji Nakamae, A1 - Hiromu Fujioka, PY - 1997 KW - automatic fault tracing system KW - EB tester KW - CAD layout KW - VLSI VL - 0 JA - Asian Test Symposium ER -

Katsuyoshi Miura, Faculty of Engineering, Osaka University

Kohei Nakata, Faculty of Engineering, Osaka University

Koji Nakamae, Faculty of Engineering, Osaka University

Hiromu Fujioka, Faculty of Engineering, Osaka University

An automatic EB fault tracing system is described which enables us to trace faults automatically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit independently of circuit functions. Only VLSI CAD layout data is required.

Index Terms:

automatic fault tracing system, EB tester, CAD layout, VLSI

Citation:

Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka, "Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data," ats, pp.162, Sixth Asian Test Symposium (ATS'97), 1997

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