An approach to diagnose logical faults in partially observable sequential circuits

Akita, JAPAN November 17-November 18

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http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643954

Sixth Asian Test Symposium (ATS'97)

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	ASCII Text	x
	K. Yamazaki, T. Yamada, "An approach to diagnose logical faults in partially observable sequential circuits," Asian Test Symposium, pp. 168, Sixth Asian Test Symposium (ATS'97), 1997.

	BibTex	x
	@article{ 10.1109/ATS.1997.643954, author = {K. Yamazaki and T. Yamada}, title = {An approach to diagnose logical faults in partially observable sequential circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1997}, issn = {1081-7735}, pages = {168}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643954}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - An approach to diagnose logical faults in partially observable sequential circuits SN - 1081-7735 SP EP A1 - K. Yamazaki, A1 - T. Yamada, PY - 1997 KW - fault diagnosis; logical faults; partially observable sequential circuits; internal nets; error sources; error propagation traceback; failing primary outputs; probing; simulation results; ISCAS'89 benchmark circuits; diagnostic resolution VL - 0 JA - Asian Test Symposium ER -

K. Yamazaki, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

T. Yamada, Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS'89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable.

Index Terms:

fault diagnosis; logical faults; partially observable sequential circuits; internal nets; error sources; error propagation traceback; failing primary outputs; probing; simulation results; ISCAS'89 benchmark circuits; diagnostic resolution

Citation:

K. Yamazaki, T. Yamada, "An approach to diagnose logical faults in partially observable sequential circuits," ats, pp.168, Sixth Asian Test Symposium (ATS'97), 1997

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