We present a high-level synthesis method that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. We introduce a design objective for weak testability that is a condition on resource sharing sufficient for weak testability. We propose a heuristic synthesis algorithm that generates a weakly testable data path while minimizing area under a performance constraint.