Alleviating DFT Cost Using Testability Driven HLS

Singapore December 02-December 04

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http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741582

Seventh Asian Test Symposium (ATS'98)

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	ASCII Text	x
	M.L. Flottes, R. Pires, B. Rouzeyre, "Alleviating DFT Cost Using Testability Driven HLS," Asian Test Symposium, pp. 46, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741582, author = {M.L. Flottes and R. Pires and B. Rouzeyre}, title = {Alleviating DFT Cost Using Testability Driven HLS}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {46}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741582}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Alleviating DFT Cost Using Testability Driven HLS SN - 1081-7735 SP EP A1 - M.L. Flottes, A1 - R. Pires, A1 - B. Rouzeyre, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

M.L. Flottes, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier

R. Pires, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier

B. Rouzeyre, Laboratoire d'Informatique, de Robotique et de Micro?lectronique de Montpellier

This paper presents a method to carry out the register allocation phase of High Level Synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area trade-off to account. It allows to decrease the cost related to the application of low-level DFT techniques.

Citation:

M.L. Flottes, R. Pires, B. Rouzeyre, "Alleviating DFT Cost Using Testability Driven HLS," ats, pp.46, Seventh Asian Test Symposium (ATS'98), 1998

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