K.-J. Lee, J.-J. Tang, W.-Y. Duh,
"On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation,"
Asian Test Symposium, pp. 113, Seventh Asian Test Symposium (ATS'98), 1998.
BibTex
x
@article{
10.1109/ATS.1998.741600, author = {K.-J. Lee and J.-J. Tang and W.-Y. Duh}, title = {On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {113}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741600}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - CONF JO - Asian Test Symposium TI - On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation SN - 1081-7735 SP EP A1 - K.-J. Lee, A1 - J.-J. Tang, A1 - W.-Y. Duh, PY - 1998 VL - 0 JA - Asian Test Symposium ER -
K.-J. Lee, J.-J. Tang, W.-Y. Duh, "On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault Simulation," ats, pp.113, Seventh Asian Test Symposium (ATS'98), 1998
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