An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits

Singapore December 02-December 04

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741613

Seventh Asian Test Symposium (ATS'98)

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Tomoo Inoue Articles by Toshinori Hosokawa Articles by Takahiro Mihara Articles by Hideo Fujiwara

	ASCII Text	x
	Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara, "An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits," Asian Test Symposium, pp. 190, Seventh Asian Test Symposium (ATS'98), 1998.

	BibTex	x
	@article{ 10.1109/ATS.1998.741613, author = {Tomoo Inoue and Toshinori Hosokawa and Takahiro Mihara and Hideo Fujiwara}, title = {An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits}, journal ={Asian Test Symposium}, volume = {0}, year = {1998}, issn = {1081-7735}, pages = {190}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741613}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits SN - 1081-7735 SP EP A1 - Tomoo Inoue, A1 - Toshinori Hosokawa, A1 - Takahiro Mihara, A1 - Hideo Fujiwara, PY - 1998 VL - 0 JA - Asian Test Symposium ER -

We present an approach to test generation using time expansion models. The tests for acyclic sequential circuits can be generated by applying combinational ATPG to our time expansion models. We made experiments on application to partial scan designed register-transfer circuits. The results show that our approach can reduce hardware overhead and test length compared with full scanwhile preserving almost 100% fault efficiency.

Citation:

Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara, "An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits," ats, pp.190, Seventh Asian Test Symposium (ATS'98), 1998

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.