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March Tests for Word-Oriented Two-Port Memories
Shanghai, China November 16-November 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810729Eighth Asian Test Symposium (ATS'99)
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Said Hamdioui, Intel Corporation and Delft University of Technology
A. J. van de Goor, Delft University of Technology
This paper presents an approach for testing word- oriented multi-port memories. Fault models for such memories are given based on fault models for bit- oriented multi-port memories. A distinction between intra-word faults and inter-word faults is made. A systematic way of converting bit-oriented multi-port memory tests into word-oriented multi-port memory tests is presented.
Citation:
Said Hamdioui, A. J. van de Goor, "March Tests for Word-Oriented Two-Port Memories," ats, pp.53, Eighth Asian Test Symposium (ATS'99), 1999
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