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Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits
Shanghai, China November 16-November 18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810731Eighth Asian Test Symposium (ATS'99)
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Zhide Zeng, Jihua Chen, Hefeng Cao, "Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits," Asian Test Symposium, pp. 70, Eighth Asian Test Symposium (ATS'99), 1999.
 
 
BibTex
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@article{ 10.1109/ATS.1999.810731,
author = {Zhide Zeng and Jihua Chen and Hefeng Cao},
title = {Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits},
journal ={Asian Test Symposium},
volume = {0},
year = {1999},
issn = {1081-7735},
pages = {70},
doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810731},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - Asian Test Symposium
TI - Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits
SN - 1081-7735
SP
EP
A1 - Zhide Zeng,
A1 - Jihua Chen,
A1 - Hefeng Cao,
PY - 1999
KW - finite backtracking test pattern generation
KW - n to 1 tightly coupled integration mode
KW - parallel-pattern
KW - single-fault propagation
KW - ultra large scale combinational circuit (ULSCC
VL - 0
JA - Asian Test Symposium
ER -
 
Zhide Zeng, National University of Defense Technology
Jihua Chen, National University of Defense Technology
Hefeng Cao, National University of Defense Technology
In this paper, a high-speed test generation method for ultra large scale combinational circuits and full-scan circuits is presented. This method adopts finite backtracking test pattern generation method to generate test pattern, and uses parallel-pattern single-fault propagating method with n (machine word length) test vectors to validate the fault coverage. The test generation and fault simulation are integrated with n to 1 tightly coupled style. The method obtains desired results: shorter test pattern length, higher fault coverage and efficiency from execution of 10 ISCAS-85 benchmark circuits.
Index Terms:
finite backtracking test pattern generation, n to 1 tightly coupled integration mode, parallel-pattern, single-fault propagation, ultra large scale combinational circuit (ULSCC
Citation:
Zhide Zeng, Jihua Chen, Hefeng Cao, "Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits," ats, pp.70, Eighth Asian Test Symposium (ATS'99), 1999
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