Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis

Taipei, Taiwan December 04-December 06

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http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893614

Ninth Asian Test Symposium (ATS'00)

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	ASCII Text	x
	S. Polonsky, M. McManus, D. Knebel, S. Steen, P. Sanda, "Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis," Asian Test Symposium, pp. 125, Ninth Asian Test Symposium (ATS'00), 2000.

	BibTex	x
	@article{ 10.1109/ATS.2000.893614, author = {S. Polonsky and M. McManus and D. Knebel and S. Steen and P. Sanda}, title = {Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis}, journal ={Asian Test Symposium}, volume = {0}, year = {2000}, issn = {1081-7735}, pages = {125}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893614}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis SN - 1081-7735 SP EP A1 - S. Polonsky, A1 - M. McManus, A1 - D. Knebel, A1 - S. Steen, A1 - P. Sanda, PY - 2000 KW - hazards and race conditions; integrated memory circuits; integrated circuit testing; timing analysis; imaging circuit analysis; IBM G6 microprocessor; L1 cache; non-invasive backside timing; Picosecond Imaging Circuit Analysis; race condition; circuit switching; waveform extraction VL - 0 JA - Asian Test Symposium ER -

S. Polonsky, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

M. McManus, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

D. Knebel, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

S. Steen, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

P. Sanda, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

The new non-invasive backside timing characterization technique, Picosecond Imaging Circuit Analysis (PICA), was applied to the identification and analysis of a race condition which occurred in an early design of the L1 cache of the S/390 microprocessor. The circuit switching activity was visualized in reconstructed slow motion videos of passing and failing conditions. An automated emission waveform extraction and analysis tool was used to perform a quantitative study of the failing condition.

Index Terms:

hazards and race conditions; integrated memory circuits; integrated circuit testing; timing analysis; imaging circuit analysis; IBM G6 microprocessor; L1 cache; non-invasive backside timing; Picosecond Imaging Circuit Analysis; race condition; circuit switching; waveform extraction

Citation:

S. Polonsky, M. McManus, D. Knebel, S. Steen, P. Sanda, "Non-invasive timing analysis of IBM G6 microprocessor L1 cache using picosecond imaging circuit analysis," ats, pp.125, Ninth Asian Test Symposium (ATS'00), 2000

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