P. Faure, LIRMM-UM2, Montpellier, France
The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault." Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.
Index Terms:
field programmable gate arrays; logic testing; integrated circuit testing; optimisation; automatic test pattern generation; TOF tool; test pattern generation optimization; FPGA application oriented test; application-oriented test procedure; RAM-based FPGAs; AC nonredundant fault coverage; circuit netlist; TPG optimisation tool; ATPG
Citation:
M. Renovell, J.M. Portal, P. Faure, J. Figueras, Y. Zorian, "TOF: a tool for test pattern generation optimization of an FPGA application oriented test," ats, pp.323, Ninth Asian Test Symposium (ATS'00), 2000
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