I/sub DDQ/ testing is an effective method for bridging faults of CMOS circuits. Since the measurement of current in I/sub DDQ/ testing takes a long time, a short test sequence is strongly desirable for reducing test application time. In this paper we present a test compaction method for an I/sub DDQ/ test sequence using a reassignment method for all bridging faults in sequential circuits. Since a large memory space is required to treat all bridging faults, an effective fault list is required. We propose the test compaction method using an assignment list of signal values. The proposed method is realized with small size memory and runs fast for many large sequential circuits. Experimental results on the benchmark circuits show that it is effective in reducing test length for given weighted random sequences.
Index Terms:
CMOS logic circuits; sequential circuits; logic testing; integrated circuit testing; fault simulation; automatic testing; memory reduction; I/sub DDQ/ test compaction; internal bridging faults; external bridging faults; CMOS circuits; test application time reduction; IDDQ test sequence; reassignment method; sequential circuits; weighted random sequences
Citation:
T. Maeda, K. Kinoshita, "Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults," ats, pp.350, Ninth Asian Test Symposium (ATS'00), 2000
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