T. Shinogi, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
M. Ushio, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
T. Hayashi, Dept. of Electr. & Electron. Eng., Mie Univ., Tsu, Japan
This paper proposes a generation method (called Cyclic Greedy generation method) of IDDQ test sets for maximizing the number of detected faults under the constraint that the number of test patterns is limited. First this method greedily generates the given limited number of test patterns, then it greedily re-generates each pattern sequentially all over again and again in a cyclic manner. Each test pattern is generated by the iterative improvement method of random patterns. The experimental results show that the number of undetected faults remained by the Cyclic Greedy generation method is 13% less than by the pure greedy generation method in average for the large ISCAS85Y circuits.
Index Terms:
integrated circuit testing; CMOS integrated circuits; electric current measurement; fault diagnosis; iterative methods; cyclic greedy generation method; IDDQ tests; test patterns; cyclic; iterative method; random patterns; undetected faults; ISCAS85Y circuits; short circuit faults; CMOS IC
Citation:
T. Shinogi, M. Ushio, T. Hayashi, "Cyclic greedy generation method for limited number of IDDQ tests," ats, pp.362, Ninth Asian Test Symposium (ATS'00), 2000
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