Specification and Design of a New Memory Fault Simulator

Guam, USA November 18-November 20

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http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181693

11th Asian Test Symposium (ATS'02)

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	ASCII Text	x
	A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, "Specification and Design of a New Memory Fault Simulator," Asian Test Symposium, pp. 92, 11th Asian Test Symposium (ATS'02), 2002.

	BibTex	x
	@article{ 10.1109/ATS.2002.1181693, author = {A. Benso and S. Di Carlo and G. Di Natale and P. Prinetto}, title = {Specification and Design of a New Memory Fault Simulator}, journal ={Asian Test Symposium}, volume = {0}, year = {2002}, issn = {1081-7735}, pages = {92}, doi = {http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181693}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Asian Test Symposium TI - Specification and Design of a New Memory Fault Simulator SN - 1081-7735 SP EP A1 - A. Benso, A1 - S. Di Carlo, A1 - G. Di Natale, A1 - P. Prinetto, PY - 2002 KW - null VL - 0 JA - Asian Test Symposium ER -

A. Benso, Politecnico di Torino

S. Di Carlo, Politecnico di Torino

G. Di Natale, Politecnico di Torino

P. Prinetto, Politecnico di Torino

This paper presents a new Fault Simulator architecture for RAM memories. The key features of the proposed tool are: 1) user-definable fault models, test algorithm, and memory architecture; 2) very fast simulation algorithm; 3) ability to compute the coverage of any provided test sequence w.r.t. a user-defined set of fault models, and to eliminate redundant operations; 4) assessment of the power consumption generated by the test application. Moreover, the tool is able to modify the test algorithm in order to guarantee the compliance to user-defined power consumption constraints.

Citation:

A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, "Specification and Design of a New Memory Fault Simulator," ats, pp.92, 11th Asian Test Symposium (ATS'02), 2002

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