In recent years, the domino logic have been received much attention. But in the case of standard domino logic, only non-inverting gates are allowed. Then, the clock-delayed (CD) domino logic that realizes any logic gate has been proposed. Moreover, the domino logic has another drawback that it is very sensitive to noise induced by crosstalk. Therefore, we focus our attention on crosstalk faults in CD domino circuits. In order to realize an efficient fault simulation, in this paper we propose a new method of a target fault reduction considering conflictions of signal values in the circuit and dominance of faults. In addition, we introduce a faster fault simulation method, which uses only logic value without handling details of timing events of circuits.